TXAK=0, IICEN=0, MST=0, TX=0, DMAEN=0, IICIE=0, WUEN=0
I2C Control Register 1
| DMAEN | DMA Enable 0 (0): All DMA signalling disabled. 1 (1): DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. |
| WUEN | Wakeup Enable 0 (0): Normal operation. No interrupt generated when address matching in low power mode. 1 (1): Enables the wakeup function in low power mode. |
| RSTA | Repeat START |
| TXAK | Transmit Acknowledge Enable 0 (0): An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). 1 (1): No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set). |
| TX | Transmit Mode Select 0 (0): Receive 1 (1): Transmit |
| MST | Master Mode Select 0 (0): Slave mode 1 (1): Master mode |
| IICIE | I2C Interrupt Enable 0 (0): Disabled 1 (1): Enabled |
| IICEN | I2C Enable 0 (0): Disabled 1 (1): Enabled |